THE ARTICLE WAS PREPARED BASED ON THE BOOK BY A. V. GOLOVKOV and V. B LYUBITSKY "POWER SUPPLY FOR SYSTEM MODULES OF THE IBM PC-XT/AT TYPE" BY THE PUBLISHING HOUSE "LAD&N"

"SLOW START" SCHEME

When you turn on the switching power supply, the output filter capacitors are not yet charged. Therefore, the transistor converter actually operates on a short-circuited load. In this case, the instantaneous power at the collector junctions of high-power transistors can exceed several times the average power consumed from the network. This is due to the fact that the feedback action at startup causes the transistor current to exceed the permissible current. Therefore, measures are necessary to ensure a “smooth” (“soft” or “slow”) start-up of the converter. In the UPS under consideration, this is achieved by smoothly increasing the duration of the on state of powerful transistors, regardless of the feedback signal, which “demands” from the control circuit the maximum possible duration of the control pulse immediately when the UPS is turned on. Those. The duty cycle of the pulse voltage at the moment of switching on is forcibly made very small and then gradually increases to the required level. “Slow start” allows the control chip IC1 to gradually increase the duration of the pulses on pins 8 and 11 until the power supply reaches nominal mode. In all UPSs based on a control IC of the TL494CN type, the “slow start” circuit is implemented using an RC circuit connected to the non-inverting input of the “dead zone” comparator DA1 (pin 4 of the microcircuit). Let's consider the operation of the starting circuit using the example of the LPS-02-150XT UPS (Fig. 41). “Slow start” is carried out in this circuit thanks to the RC circuit C19, R20 connected to pin 4 of the control chip IC1.
Before considering the operation of the “soft start” circuit, it is necessary to introduce the concept of the UPS startup algorithm. The startup algorithm refers to the sequence in which voltages appear in the UPS circuit. In accordance with the physics of operation, the rectified network voltage Uep always appears initially. Then, as a result of the triggering circuit, the supply voltage to the Upom control chip appears. The result of applying power to the microcircuit is the appearance of the output voltage of the internal stabilized reference voltage Uref. Only after this the output voltages of the block appear. The sequence of appearance of these stresses cannot be disrupted, i.e. Uref, for example, cannot appear earlier than Upom, etc.
Note We draw your special attention to the fact that the process of initial startup of the UPS and the “slow start” process are different processes that occur sequentially over time! When the UPS is connected to the network, first there is an initial start-up, and only then a “slow start”, which makes it easier for the power transistors of the unit to reach the nominal mode.
As already noted, the ultimate goal of the “slow start” process is to obtain output control pulses at pins 8 and 11 that smoothly increase in width. The width of the output pulses is determined by the width of the pulses at the output of logic element DD1 IC1 (see Fig. 13). The flow of the UPS soft start process over time is shown in Fig. 47.
Let at time t0 the control chip IC1 be supplied with supply voltage Upom. As a result, the sawtooth voltage generator DA6 is started, and the reference voltage Uref appears at pin 14. The generator's sawtooth output voltage is supplied to the inverting inputs of comparators DA1 and DA2. The inverting input of the PWM comparator DA2 is supplied with the output voltage of the error amplifier DA3. Since the output voltages of the block (including +5V) are not yet available, the feedback signal taken from the divider R19, R20 and supplied to the non-inverting input of the error amplifier is equal to 0. A certain positive voltage is supplied to the inverting input of this amplifier, which is removed from divider SVR, R24, R22 in the reference voltage bus circuit Uref, which is already available. Therefore, the output voltage of the error amplifier DA3 will be equal to 0 at the initial moment, and as the output capacitors of the filters are charged, it will increase. For this reason, the output voltage of the PWM comparator DA2 will be a sequence of pulses increasing in width. This process is shown in time diagrams 1 and 2 (Fig. 47).

Figure 47. Timing diagrams explaining the process of smooth (soft) startup of the UPS and illustrating the operation of the control HMCTL494 in startup mode: U3, U4, U5 - voltages at IC pins 3, 4 and 5, respectively.

The non-inverting input of the deadband comparator DA1 is connected to pin 4 of IC1. An external RC circuit C19, R20 is connected to this pin, which is powered from the reference voltage bus Uref. Therefore, when Uref appears, all of it is allocated at the first moment on resistor R20, because capacitor C19 is completely discharged. As C19 charges, the current through it and resistor R20 decreases. Therefore, the voltage drop across R20, which is applied to pin 4 of 1C 1, has the form of a decaying exponential. In accordance with this, the output voltage of the “dead zone” comparator DA1 will be a sequence of pulses decreasing in width. This process is shown in time diagrams 3 and 4 (Fig. 47). Thus, the processes of latitudinal changes in the output voltages of comparators DA1 and DA2 are mutually opposite in nature.
The output voltages of the comparators are input to the DD1 (2-OR) logic element. Therefore, the pulse width at the output of this element is determined by the widest of the input pulses.
From timing diagram 5 (Fig. 47), displaying the output voltage of DD1, it is clear that up to the moment ti, the width of the output pulses of the comparator DA1 exceeds the width of the output pulses of the PWM comparator DA2. Therefore, switching this comparator does not affect the width of the output pulse DD1, and therefore the output pulse IC1. The determining factor in the to-t-i interval is the output voltage of comparator DA1. The width of the output pulses IC1 smoothly increases in this interval, as can be seen from timing diagrams 6 and 7 (Fig. 47).
At time ti, the output pulse of comparator DA1 is compared in width with the output pulse of PWM comparator DA2. At this moment, control is transferred from comparator DA1 to PWM comparator DA2, because its output pulses begin to exceed the width of the output pulses of the comparator DA1. During the time t0-t, the output capacitors of the filters manage to smoothly charge, and the unit manages to enter the nominal mode.
Thus, the essence of the circuit solution to the “soft” start-up problem is that while charging the capacitors of the output filters, the PWM comparator DA2 is replaced by the comparator DA1, the operation of which does not depend on the feedback signal, but is determined by a special forming RC circuit C19.R20.
From the material discussed above, it follows that before each UPS is turned on, the capacitor of the forming RC circuit (in this case C19) must be completely discharged, otherwise a “soft” start will be impossible, which can lead to failure of the power transistors of the converter. Therefore, each UPS circuit has a special circuit for quickly discharging the capacitor of the forming circuit when the UPS is turned off from the network or when the current protection is triggered.

PG SIGNAL PRODUCTION CIRCUIT (POWER GOOD)

The PG signal, along with the four output voltages of the system unit, is the standard output parameter of the UPS.
The presence of this signal is mandatory for any block that complies with the IBM standard (and not just blocks built on the TL494 chip). However, in XT class computers this signal is sometimes not used.
In UPS there is a wide variety of PG signal generation schemes. Conventionally, the entire variety of schemes can be divided into two groups: one non-functional and two-functional.
One non-functional circuit implements only the function of delaying the appearance of the H-level PG signal that allows the processor to start when the UPS is turned on.
Dual-function circuits, in addition to the above function, also implement the function of proactively transitioning the PG signal to an inactive low level, which prohibits the processor from operating when the UPS is turned off, as well as in cases of various types of emergency situations, before the +5V voltage supplying the digital part of the system module begins to decrease.
Most PG signal generation circuits are dual-function, but they are more complex than the first type.

Figure 48. Functional diagram of the LM339 IC (top view).

Figure 49. Schematic diagram of one comparator IC LM339.

Figure 50. Diagram of PG signal generation in the GT-200W UPS

The LM339N type microcircuit, which is a quad voltage comparator, is widely used as a basic element in the construction of these circuits (Fig. 48).
The output transistors of each comparator have an open collector (Fig. 49). Pin 12 of the LM339N is connected to the “case”, and pin 3 is supplied with unipolar (from +2V to +ZOV) power.
Thanks to the high sensitivity of comparator circuits, the required speed is ensured.
Let's take a closer look at several typical options for constructing PG signal generation circuits.
The PG signal generation circuit used in the GT-200W unit is shown in Fig. 50.

When the unit is connected to the network, the starting circuit is triggered and a reference voltage of +5.1V appears on the Uref bus from the internal source of the TL494 microcircuit. There is no +5V output voltage yet. Therefore, the feedback divider R25, R24 is not yet energized (the potential of pin 1 of the microcircuit is 0V). The divider, which provides the reference level at pin 2 of the microcircuit, is already powered by voltage Uref. Therefore, the output voltage of the error amplifier is minimal (at pin 3 the potential is about 0V), and transistor Q7, powered by the same voltage Uref from the collector, is open and saturated with the base current flowing through the circuit: Uref - R36 - e-6 Q7 - R31 - internal circuits TL494 - "frame".
The potential of the non-inverting input of comparator 1 of IC2 (LM339N) is 0, and since at its inverting input there is a positive potential from resistor R42 of the divider R35, R42 in the Uref circuit, the comparator itself will be in the 0V state at the output (the output transistor of the comparator is open and saturated). Therefore, the PG signal is L-level and prohibits the processor from operating.
Next, the +5V output voltage begins to appear as the high-capacity output capacitors charge. Therefore, the output voltage of the error amplifier DA3 begins to increase, and the transistor Q7 turns off. As a result, the retention tank C16 begins to become infected. The charging current flows through the circuit: Uref -R36- C16- “housing”.
As soon as the voltage at C16 and at the non-inverting input of comparator 1 (pin 7 of IC2) reaches the reference level at its inverting input (pin 6 of IC2), the output transistor of the comparator will close. The PIC, which covers comparator 1 (resistor R34), determines the presence of hysteresis on the transfer characteristic of this comparator. This ensures reliable operation of the PG circuit and eliminates the possibility of the comparator “rolling over” under the influence of random impulse noise (noise). At this point, the full rated voltage appears on the +5V bus, and the PG signal becomes an H-level signal.
From the above it can be seen that the block status sensor (on/off) in this circuit is the output voltage of the error amplifier DA3, taken from pin 3 of the control chip IC1 (TL494), and the circuit is single-functional.
A more complex scheme for generating a PG signal is implemented in the APPIS UPS (Fig. 51).

Figure 51. Scheme of PG signal generation in the Appis UPS.

This circuit uses three comparators of IC2.
The power-on delay function is implemented as follows.
After the UPS is connected to the network and the starting circuit is activated, the reference voltage Uref appears. There are no output voltages from the unit yet. Therefore, IC2 and transistor Q3 are not yet energized. Transistor Q4, from the collector of which the PG signal is removed, is open because its base divisor is written down. The base current flows through the circuit: Uref- R34 - R35 -6-3Q4- “housing”.
Therefore PG is L-level. In addition, capacitor C21 is charged from the Uref bus through the circuit: Uref-R29-C21 - “housing”.
With the appearance of the block’s output voltages, microcircuit IC2 and transistor Q3 are powered from the +12V bus through the decoupling filter R38, C24. From the +5V bus, transistor Q4 is supplied with full voltage through the collector. In this case, the following processes occur.
Starting from the moment the unit is turned on, the inverting input of the controlling comparator receives the unsmoothed voltage rectified by the full-wave circuit D5, D6 from the secondary winding 3-4-5 of a special transformer T1. This pulsating voltage with an amplitude of about 15V is supplied to the inverting input of comparator 2 through the amplitude limitation link R24, ZD1 (11V Zener diode) and resistive divider R25, R26. Since the amplitude of the pulses after limiting and dividing still remains greater than the reference voltage level at the non-inverting input of comparator 2, then with each pulse and for almost the entire duration of its action, comparator 2 is transferred to the 0V output state (the output transistor of the comparator will be open). Therefore, within a few pulses, the delay capacitor C21 is discharged to almost 0V. Therefore, comparator 1 switches the output to state 0V, because the voltage at its non-inverting input is determined by the voltage level at capacitor C21. As a result, transistor Q3 is turned off with zero bias. Locking Q3 leads to charging of the second delay capacitor C23 along the circuit: + 12V - R38 - R32 - R33 - C23 - “housing”.
As soon as the voltage at the collector Q3, and therefore at the inverting input of comparator 3, reaches the threshold level at its inverting input (Uref = +5.1V), comparator 3 switches to the 0V output state (the output transistor of the comparator opens). Therefore, the base divider R35, R36 for Q4 will be unpowered, and Q4 will be disabled.
Since full voltage is already present on the +5V bus, and Q4 is locked, the PG signal becomes H-level.
The power-off preemption function is implemented as follows.
When the unit is turned off from the network, the rectified voltage immediately stops flowing from the secondary winding 3-4-5 TL and the rectification circuit D5, D6. Therefore, comparator 2 immediately switches, its output transistor closes. Next, the delay capacitance C21 begins to charge from Uref through R29. This prevents the circuit from triggering during random short-term dips in the mains voltage. When C21 is charged to half the voltage Uref, comparator 1 will switch. Its output transistor will turn off. Then transistor Q3 will open with the base current flowing through the circuit: +726 - R38 - R31 -D21-6-9Q3- “housing”.
The capacitance of the second delay C23 is quickly discharged through Q3 and the accelerating diode D20 along the circuit: (+)C23 - D20 - capacitor Q3 - “case” - (-)C23.
The potential of the inverting input of comparator 3 will quickly decrease with the discharge rate of C23. Therefore, comparator 3 will switch, its output transistor will close, and the base divider for Q4 will be powered from the Uref bus. Therefore, Q4 will open to saturation, and the PG signal will become L-level, warning the digital part of the system unit about the impending disappearance of the supply voltage.
Thus, in this circuit, the block state sensor (on/off) is the presence or absence of transformed mains voltage (through transformer T1), and the circuit is dual-functional.
The KYP-150W power supply uses a PG signal generation circuit using two comparators of the LM339N microcircuit (Fig. 52).

Rice. 52. Scheme of PG signal generation in the KYP-150W UPS (TUV ESSEN FAR EAST CORP.).

In this circuit, the block state sensor is the level of the auxiliary supply voltage Upom of the TL494 chip.
The scheme works as follows. When the UPS is connected to the network, the starting circuit is activated, as a result of which voltage appears on the Upon bus, which powers the TL494 control chip. As soon as Upom reaches a level of about +7V, the microcircuit starts up and the output voltage of the internal reference source Uref = +5V appears at pin 14 of it. There are no output voltages from the unit yet. Microcircuit IC2 (LM339N) is powered by voltage Uref at pin 3.
When Upom reaches a level of about +12V, the zener diode ZD1 “breaks through”, and a voltage drop appears across resistor R34, which increases with increasing Upom. When the drop across R34 reaches the level of the reference voltage across the resistor R48 of the divider R51, R48 in the Uref circuit, comparator 2 of the IC2 chip will be set to the H-level output state (its output transistor will close). Therefore, diode D22 will be locked. The charge of the delay capacitance C15 begins along the circuit: Uref- R49- C15- “housing”
This process introduces a delay in the “rolling over” of comparator 1 of the IC2 chip and the appearance of the H-level enabling signal PG. During this time, the “soft” start-up process has time to occur, and the output voltages of the unit appear in full, i.e. the unit reliably returns to nominal mode. As soon as the voltage at C15 reaches the reference level at resistor R48, comparator 1 will flip over. Its output transistor will open, and therefore transistor Q7 will be zero biased. The PG signal removed from the collector load Q7 will become H-level, which will allow the system module processor to start.
When the unit is turned off from the network, the Upom voltage begins to disappear first, because The storage capacitors that maintain voltage on the Uporn bus have a small capacitance. As soon as the voltage drop across resistor R34 falls below the reference level across resistor R48, comparator 2 of IC2 will switch. Its output transistor will open, and through it and diode D22 the delay capacitance C15 will quickly discharge. The discharge occurs almost instantly, because There is no limiting resistance in the discharge current flow circuit. Immediately after this, comparator 1 of the IC2 chip will switch. The PIC through diode D21, covering comparator 1, causes the presence of hysteresis on the transient response of the comparator. The output transistor of the comparator will close and the base current flowing through the circuit: Uref - R50 - 6th Q7 - "case", the transistor Q7 will open. The PG signal will become L-level, preventing the impending disappearance of the unit’s output voltages. Thus, this scheme is dual-functional.
The GT-150W UPS uses a PG signal generation circuit that implements only the turn-on delay function (Fig. 53).

Figure 53. Diagram of PG signal generation in the GT-150W UPS

After the IVP is turned on and the starting circuit is activated, voltages begin to appear on the output buses of the unit. Capacitor C23 begins to charge through the circuit: bus +56 - C23 - R50 - 6th Q7 - "body".
This current opens transistor Q7 until saturation, from the collector of which the PG signal is removed. Therefore, the PG signal will be at L-level almost the entire time the C23 is charging. As soon as the voltage on the +5V bus stops increasing, reaching the nominal level, the charging current C23 stops flowing. Therefore Q7 will close and the PG signal will become an H-level signal.
Diode D16 is necessary for quick and reliable discharge of C23 after turning off the UPS.
Thus, PG signal generation schemes can be classified according to the physical principle underlying their construction:
circuits built on the basis of monitoring the output voltage of the internal voltage error amplifier DA3 of the control chip or (which is the same) monitoring the level of the feedback signal from the +5V output voltage bus;
circuits built on the basis of level control and the presence of alternating mains voltage at the input of the unit;
circuits built on the basis of monitoring the level of auxiliary supply voltage of the Upom control chip.
circuits built on the basis of monitoring the presence of pulsed alternating high-frequency voltage on the secondary side of a power pulse transformer.
Let's consider one of the options for implementing the latter type of circuit, which is used, for example, in the HPR-200 UPS circuit (Fig. 54). The construction of this circuit is based on the idea of ​​​​controlling the presence of alternating pulse voltage on the secondary winding of the power pulse transformer T1. The scheme works as follows.

Figure 54. Diagram of PG signal generation in the HPR-200 UPS (HIGH POWER ELECTRONIC Co., Ltd)

When the UPS is connected to the network, the smoothing capacitors of the +5V output voltage bus C4, C5 of large capacity (2x33Omkf) are completely discharged. Capacitors C1, C2, SZ are also discharged. The pulse alternating voltage, which appears on the secondary winding 3-5 of the power pulse transformer T1, begins to charge capacitors C4, C5. A half-wave rectifier D1 is connected to tap 5 of the secondary winding. C1 - filter smoothing capacity. R1 (10 Ohm) - current-limiting resistor. Capacitor C1 of small capacity (150nf) is charged to a level of about +10V almost immediately (with the first pulse).
As soon as the potential level of the +5V bus exceeds the minimum permissible voltage supply level for the IC1 microcircuit (+2V), the microcircuit will begin to function. The voltage from capacitor C1 is supplied to resistive divider R2, R3. Part of this voltage is removed from R3 and supplied to the non-inverting input of comparator A (pin 9 of IC1), as well as to the divider R4, R6, C2. Therefore, in parallel with the increase in the potential of the +5V bus, capacitor C2 is charged along the circuit: (+)C1 - R2 - R4 - C2 - “case” - (-)C1.
By the time the +5V bus potential reaches the minimum power supply level for IC1 (+2V), this capacitor will be charged. Therefore, the comparators of the chip are set to the following state:
comparator A - the output transistor is closed, because the potential of the non-inverting input is higher than the potential at the inverting input;
comparator B - the output transistor is open, because The potential of the non-inverting input is lower than the potential of the inverting input.
This potential distribution is determined by the values ​​of the resistors connected to the inputs of the comparators.
The PG signal, removed from the collector load R11 of the output transistor of comparator B, is equal to 0V and prohibits the processor from starting. In the meantime, the process of recharging storage capacitors C4, C5 is underway and the potential of the +5V bus increases. Therefore, the charge current of the capacitor SZ flows through the circuit: bus +56 - R9 - R8 - SZ - “housing”.
The voltage at capacitor SZ, and therefore at the non-inverting input of comparator B, increases. This increase occurs until the potential of the non-inverting input of comparator B begins to exceed the potential of its inverting input. As soon as this happens, comparator B switches and its output transistor closes. The voltage on the +5V bus reaches the nominal level at this point. Therefore, the PG signal becomes a high level signal and allows the processor to start. Thus, the capacitance of the capacitor SZ causes a delay when turning on.
When you turn off the switching power supply from the network, the alternating pulse voltage on the secondary winding 3-5 T1 disappears. Therefore, the small capacitor C1 quickly discharges, and the voltage at the non-inverting input of comparator A quickly decreases to 0V. The voltage at the inverting input of this comparator drops much more slowly due to the charge on capacitor C2. Therefore, the potential of the inverting input becomes higher than the potential of the non-inverting input, and comparator A switches. Its output transistor opens. Therefore, the potential of the non-inverting input of comparator B becomes 0V. The potential of the inverting input of comparator B is still positive due to the charge on capacitor C2. Therefore, comparator B switches, its output transistor opens and the PG signal becomes a low level signal, initializing the system reset signal RESET, before the +5 V supply voltage to the logic chips decreases below the permissible level.
Comparators A and B are covered by positive feedback using resistors R7 and R10, respectively, which speeds up their switching.
Precision resistive divider R5, R6 sets the reference voltage level at the inverting inputs of comparators A and B in the nominal operating mode.
Capacitor C2 is required to maintain this reference level after the UPS is turned off from the network.
To conclude this section, we present another implementation option for the PG signal generation circuit (Fig. 55).

Figure 55. Scheme of PG signal generation in the SP-200W UPS.

The circuit is single-functional, i.e. implements only a delay in the appearance of the enabling signal PG when the IVP is connected to the network.
In this circuit, the controlled signal is the voltage level on the +12V channel output bus. The circuit is based on a two-stage UPT circuit using transistors Q10, Q11, covered by positive feedback using resistor R55. The rollover delay of this circuit is due to the presence of a relatively large capacitance capacitor C31 in the base circuit of the transistor Q10 of the UPT. After connecting the UPS to the network, while the process of entering the mode is ongoing, a charging current of capacitor C31 flows from the output bus of the +12V channel through the circuit: +12V bus -R40-C31 - “case”.
The voltage on capacitor C31 gradually increases. Until this voltage reaches the threshold level for stalling the circuit on transistors Q10, Q11, this circuit is in a state in which transistor Q10 is closed and transistor Q11 is open by the base current that flows from the +5V channel output bus under the influence of the growing voltage on the capacitors of this bus : bus +56 - R41 - 6th Q11 - "body".
Therefore, the PG signal taken from the Q11 collector is 0V and prohibits the processor from starting. Meanwhile, an increasing voltage across capacitor C31 is applied to the base divider R43, R44 of transistor Q10. By the time the output voltages of the UPS reach nominal levels, the voltage on C31 will reach a level sufficient for the occurrence of an avalanche-like process of mutual changes in the states of transistors Q10, Q11 (due to the presence of PIC). As a result, transistor Q10 will be open to saturation, and transistor Q11 will be closed. Therefore, the PG signal will become a high level signal and the processor will be allowed to start. Diode D20 serves to quickly discharge capacitor C31 after turning off the UPS from the network. In this case, C31 is discharged through diode D20 and the discharge resistor of the +5V channel output bus (not shown in the diagram). In addition, during operation of the UPS, this diode limits the voltage level on capacitor C31. The limit level is about +5.8V.
In addition to the above PG signal generation schemes, other principles of circuit design can be used, and a different number of comparators of the LM339N chip can be used - from one to four.

BASIC PARAMETERS OF SWITCH POWER SUPPLY FOR IBM		The main parameters of switching power supplies are considered, the connector pinout is given, the principle of operation on mains voltage is 110 and 220 volts,
		The TL494 microcircuit, switching circuit and use cases for controlling power switches of switching power supplies are described in detail.
MANAGING POWER SWITCHES OF A SWITCHING POWER SUPPLY USING TL494		The main methods for controlling the basic circuits of power transistors in switching power supplies and options for constructing secondary power rectifiers are described.
STABILIZATION OF OUTPUT VOLTAGES OF PULSE POWER UNITS		Options for using error amplifiers TL494 to stabilize output voltages are described, and the operating principle of a group stabilization choke is described.
PROTECTION SCHEMES		Several options for constructing systems for protecting pulsed power supplies from overload are described.
"SLOW START" SCHEME		The principles of forming a soft start and generating POWER GOOD voltage are described
EXAMPLE OF CONSTRUCTION OF ONE OF THE PULSE POWER SUPPLY SUPPLY		A complete description of the circuit diagram and its operation of a switching power supply

When designing amplifier power supplies Often problems arise that have nothing to do with the amplifier itself, or that are a consequence of the used element base. So in power supplies transistor amplifiers With high power, the problem often arises of implementing a smooth switching on of the power supply, that is, ensuring a slow charge of electrolytic capacitors in the smoothing filter, which can have a very significant capacity and, without taking appropriate measures, will simply damage the rectifier diodes at the moment of switching on.

In power supplies for tube amplifiers of any power, it is necessary to provide a feed delay high anode voltage before warming up the lamps, in order to avoid premature depletion of the cathode and, as a result, a significant reduction in the lamp life. Of course, when using a kenotron rectifier, this problem is solved by itself. But if you use a conventional bridge rectifier with an LC filter, you cannot do without an additional device.

Both of the above problems can be solved by a simple device that can be easily built into both a transistor and a tube amplifier.

Device diagram.

The schematic diagram of the soft start device is shown in the figure:

Click to enlarge

The alternating voltage on the secondary winding of transformer TP1 is rectified by the diode bridge Br1 and stabilized by the integrated stabilizer VR1. Resistor R1 ensures smooth charging of capacitor C3. When the voltage across it reaches a threshold value, transistor T1 will open, causing relay Rel1 to operate. Resistor R2 ensures the discharge of capacitor C3 when the device is turned off.

Inclusion options.

The Rel1 relay contact group is connected depending on the type of amplifier and the organization of the power supply.

For example, to ensure smooth charging of capacitors in the power supply transistor power amplifier, the presented device can be used to bypass the ballast resistor after charging the capacitors in order to eliminate power losses on it. A possible connection option is shown in the diagram:

The values ​​of the fuse and ballast resistor are not indicated, since they are selected based on the power of the amplifier and the capacitance of the smoothing filter capacitors.

In a tube amplifier, the presented device will help organize a feed delay high anode voltage before the lamps warm up, which can significantly extend their service life. A possible inclusion option is shown in the figure:

The delay circuit here is turned on simultaneously with the filament transformer. After the lamps have warmed up, relay Rel1 will turn on, as a result of which the mains voltage will be supplied to the anode transformer.

If your amplifier uses one transformer to power both the lamp filament circuits and the anode voltage, then the relay contact group should be moved to the secondary winding circuit anode voltage.

Elements of the switch-on delay circuit (soft start):

• Fuse: 220V 100mA,
• Transformer: any low-power with an output voltage of 12-14V,
• Diode bridge: any small-sized one with parameters 35V/1A and higher,
• Capacitors: C1 - 1000uF 35V, C2 - 100nF 63V, C3 - 100uF 25V,
• Resistors: R1 - 220 kOhm, R2 - 120 kOhm,
• Transistor: IRF510,
• Integral stabilizer: 7809, LM7809, L7809, MC7809 (7812),
• Relay: with an operating winding voltage of 9V (12V for 7812) and a contact group of the appropriate power.

Due to the low current consumption, the stabilizer chip and field-effect transistor can be mounted without radiators.

However, someone may have the idea to abandon the extra, albeit small-sized, transformer and power the delay circuit from the filament voltage. Considering that the standard value of the filament voltage is ~6.3V, you will have to replace the L7809 stabilizer with an L7805 and use a relay with a winding operating voltage of 5V. Such relays usually consume significant current, in which case the microcircuit and transistor will have to be equipped with small radiators.

When using a relay with a 12V winding (somehow more common), the integrated stabilizer chip should be replaced with a 7812 (L7812, LM7812, MC7812).

With the values ​​of resistor R1 and capacitor C3 indicated in the diagram delay time inclusions are of the order 20 seconds. To increase the time interval, it is necessary to increase the capacitance of capacitor C3.

The article was prepared based on materials from the magazine "Audio Express"

Free translation by the Editor-in-Chief of RadioGazeta.

The article uses materials from an article by Alexey Efremov. I had the idea of ​​developing a soft start device for a power supply a long time ago, and at first glance it should have been implemented quite simply. An approximate solution was proposed by Alexey Efremov in the above-mentioned article. He also based the device on a key based on a powerful high-voltage transistor.

The chain to the key can be represented graphically like this:

It is clear that when SA1 is closed, the primary winding of the power transformer is actually connected to the network. Why is there a diode bridge at all? - to provide direct current power to the switch on the transistor.

Circuit with transistor switch:

The given ratings of the divider are somewhat confusing... although the hope that the device will not smoke or bang remains, doubts arise. And yet I tried a similar option. Only I chose a more harmless power supply - 26V, of course, I chose other resistor values, and used not a transformer as a load, but a 28V/10W incandescent lamp. And the key transistor used BU508A.

My experiments have shown that a resistor divider successfully lowers the voltage, but the current output of such a source is very small (the BE junction has low internal resistance), and the voltage across the capacitor drops significantly. I didn’t risk infinitely reducing the value of the resistor in the upper arm, in any case - even if we find the correct current distribution in the arms and the transition is saturated, it will still be only a softened, but not a smooth start.

In my opinion, a truly soft start should occur in at least 2 stages; First, the key transistor opens slightly - a couple of seconds will be enough for the filter electrolytes in the power supply to be recharged with a weak current. And at the second stage it is already necessary to ensure the complete opening of the transistor. The circuit had to be somewhat complicated; in addition to dividing the process into 2 stages (stages), I decided to make the switch composite (Darlington circuit) and as a source of control voltage, I decided to use a separate low-power step-down transformer.

*Ratings of resistor R 3 and trimmer R 5. To obtain a circuit supply voltage of 5.1V, the total resistance R 3 + R 5 must be 740 Ohms (with R 4 = 240 Ohms selected). For example, to ensure adjustment with a small margin, R 3 can be taken 500-640 Ohm, R 5 - 300-200 Ohm, respectively.

I believe there is no particular need to describe in detail how the scheme works. In short, the first stage is launched by VT4, the second is launched by VT2, and VT1 provides a delay in switching on the second stage. In the case of a “rested” device (all electrolytes are completely discharged), the first stage starts after 4 seconds. after turning on, and after another 5 seconds. the second stage starts. If the device is disconnected from the network and turned on again; the first stage starts after 2 seconds, and the second - after 3...4 seconds.

A little tweaking:

The whole setup comes down to setting the open circuit voltage at the stabilizer output, set it by rotating R5 to 5.1 V. Then connect the stabilizer output to the circuit.

You can also choose the value of resistor R2 to your taste - the lower the value, the more the key will be open at the first stage. At the nominal value indicated in the diagram, the voltage at the load = 1/5 of the maximum.

And you can change the capacitances of capacitors C2, C3, C4 and C5 if you want to change the turn-on time of the stages or the turn-on delay of the 2nd stage. The BU508A transistor must be installed on a heat sink with an area of ​​70...100mm2. It is advisable to equip the remaining transistors with small heat sinks. The power of all resistors in the circuit can be 0.125W (or more).

Diode bridge VD1 - any ordinary one for 10A, VD2 - any ordinary one for 1A.

The voltage in the secondary winding TR2 is from 8 to 20V.

Interesting? Need a signet or practical recommendations?

To be continued...

*The name of the topic on the forum must correspond to the form: Article title [article discussion]

M. SIRAZETDINOV, Ufa
Radio, 2000, No. 9

When assembling powerful ULFs, the question always arises about protection against impulse overloads at the moment of switching on. As a rule, the output stage of any powerful amplifier is powered from a bipolar source in which very large capacitors are installed (up to 10,000 μF and sometimes even higher). When the power supply is turned on, a very large charging current begins to flow through them, which creates a significant load on the power source itself, and this is also not very good for the output stage...

The way out is the so-called “soft” start: smooth supply of mains voltage to the mains transformer. Quite a lot of devices have been considered in the literature and another of them is presented here.

Its main distinctive feature is that here the increase in mains voltage occurs really smoothly, and not stepwise as in many similar devices.

Device diagram for soft switching on ULF

Fundamental circuit diagram of the UMZCH “soft” power-on device shown in the figure. Transistor VT1 through the diode bridge VD1-VD4 is connected in series with the primary winding of transformer T1 of the power supply. The choice of a MOSFET with an insulated gate is due to the high input impedance of its control circuit, which reduces power consumption.

The control unit consists of circuits that generate voltage at the gate of transistor VT1, and an electronic switch on transistors VT2, VT3. The first circuit is formed by elements VD5, C1, R1 - R3, VD7, C4, which set the initial voltage at the gate of transistor VT1. The second includes elements VD8, R4, R5, C2, SZ, which ensure a smooth increase in voltage at the gate of transistor VT1. Zener diode VD6 limits the voltage at the gate of transistor VT1 and protects it from breakdown.

In the initial state, the capacitors of the control unit circuits are discharged, therefore, at the moment the contacts of the mains power switch SB1 are closed, the voltage at the gate of transistor VT1 relative to its source is zero and there is no current in the source-drain circuit. This means that the current in the primary winding of transformer T1 and the voltage drop across it are also zero. With the arrival of the first positive half-cycle of the mains voltage, capacitor C1 begins to charge through the circuit VD5, VD3 and during this half-cycle it is charged to the amplitude value of the mains voltage.

Zener diode VD7 stabilizes the voltage on the divider R2R3. The voltage on the lower arm of trimming resistor R3 in the circuit determines the initial gate-source voltage of transistor VT1, which is set close to the threshold value of 2...4 V. After several periods of mains voltage, current pulses flowing through capacitor C2 will charge it to voltage exceeding the cutoff voltage of transistor VT3.

The electronic switch on transistors VT2, VT3 closes, and the capacitor SZ begins to charge through the circuit VD8, R4, R5, R3, VD3. The gate-source voltage of transistor VT1 is determined at this time by the sum of the voltage on the lower arm of resistor R3 and the gradually increasing voltage on capacitor SZ. As this voltage increases, transistor VT1 opens and the resistance of its source-drain channel becomes minimal. Accordingly, the voltage on the primary winding of transformer T1 smoothly increases almost to the value of the mains voltage. A further increase in the gate-source voltage of transistor VT1 is limited by the zener diode VD6. In steady state, the voltage drop across the diodes of the bridge VD1-VD4 and transistor VT1 does not exceed 2...3 W, so this practically does not affect the further operation of the UMZCH power supply. The duration of the most severe operating mode of transistor VT1 does not exceed 2...4 s, so the power dissipated by it is small. Capacitor C4 eliminates voltage ripple at the gate-source junction of transistor VT1. created by pulses of the charging current of the capacitor SZ on the lower arm of resistor R3.

An electronic switch on transistors VT2, VT3 quickly discharges the capacitor SZ after turning off the UMZCH power supply or during short-term interruptions in the power supply and prepares the control unit for restart.

The author's version of the protection device uses an imported capacitor manufactured by Gloria (C1), as well as domestic ones: K53-1 (C2, C4) and K52-1 (SZ). All fixed resistors are MLT, trimming resistor R3 is SP5-3. Transistor KP707V (VT1) can be replaced with another, for example. KP809D. It is important that the resistance of its channel in the open state is minimal, and the maximum source-drain voltage is at least 350 V. Instead of the KT3102B (VT2) transistor, it is permissible to use KT3102V and KT3102D, and instead of KP103I (VTЗ) - KP103Zh.

Transistor VT1 is equipped with a small heat sink with an area of ​​10...50 cm 2.

Setting up the device consists of selecting the optimal position of the trimmer resistor R3. Initially, it is installed in the lower (according to the diagram) position and connected through a high-resistance divider to the primary winding of the transformer

T1 oscilloscope. Then the contacts of switch SB1 are closed and, by moving the slider of resistor R3. observe the process of increasing voltage amplitude on the primary winding of the transformer. The engine is left in a position in which the time interval between turning on SB1 and the beginning of the increase in the voltage amplitude on the T1 winding is minimal. If necessary, you should select the capacitance of the capacitor SZ.

The device was tested with a prototype UMZCH, similar in structure to the amplifier described in the article by A. Orlov “UMZCH with single-stage voltage amplification” (see “Radio”. 1997, No. 12, pp. 14 - 16). The voltage surge at the output of the UMZCH when the power supply was turned on did not exceed 1.5 V